A multi-chip package (MCP) includes two or more silicon die adapted in a single package. Sometimes the chips in a single package communicate with each other using a standard serial interface like a Peripheral Component Interconnect Express™ interconnect in accordance with the PCI Express™ Specification Base Specification version 2.0 (published Jan. 17, 2007) (hereafter the PCIe™ Specification) or another such protocol. These interfaces would typically be externally visible (i.e., outside the package) if the dies were packaged individually. However in an MCP as these interfaces are not coupled to the external package, the visibility of the interfaces is lost at the package level. One solution is to provide dedicated pins on the package to enable observability of these interfaces to the external world, e.g., for post-silicon debug. Considering the differential nature of these interfaces, sometimes 50-100 dedicated pins are needed on the package to obtain complete visibility. Another option is to provide bumps on the top of the package to enable interconnection with this internal link. The former solution can raise the complexity of routing of interconnection pins, while the latter solution can mandate the need for additional layers of the die. Either option increases the amount of connections and package real estate and thus raises costs.